A recently developed semiconductor package is known as a "chip scale package" or a "chip size package". The dice contained in these packages are referred to as being "minimally packaged". Chip scale packages can be constructed in "cased" or "uncased" configurations. Cased chip scale packages have a peripheral outline that is slightly larger that an unpackaged die. Uncased chip scale packages have a peripheral outline that is about the same as an unpackaged die.
Typically, a cased chip scale package includes a substrate formed of plastic, ceramic, or other electrically insulating material bonded to the face of the die. The substrate can include external contacts for making outside electrical connections to the chip scale package. For example, the external contacts for a chip scale package can comprise contact bumps arranged in a ball grid array (BGA), or a fine ball grid array (FBGA). Typically, the external contacts comprise a solder material, that permits the chip scale package to be flip chip bonded to a printed circuit board, or other substrate. Uncased chip scale packages can include external contacts formed directly on the device bond pads in the manner of a bumped die.
Following the manufacturing process, chip scale packages must be tested and burned-in. Test apparatus can be used to house one or more chip scale packages for testing, and to make temporary electrical connections with the external contacts on the chip scale packages. The test apparatus can include an interconnect component having contact members adapted to make the temporary electrical connections with the external contacts on the chip scale packages.
For making the electrical connections the contact members on the interconnect must be aligned with the external contacts on the chip scale packages. One method of alignment is with an optical alignment system such as described in U.S. Pat. No. 5,634,267 to Wood et al. Another method of alignment is with a mechanical alignment system.
The present invention is directed to a test system with an improved mechanical alignment system. The test system can be used to test chip scale packages or other semiconductor components such as bare semiconductor dice.